In the semiconductor production industry, various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include the deposition of layers of different materials including metallization layers, passivation layers and insulation layers on the wafer substrate, as well as photoresist stripping and sidewall passivation polymer layer removal. In modern memory devices, for example, multiple layers of metal conductors are required for providing a multi-layer metal interconnection structure in defining a circuit on the wafer. Chemical vapor deposition (CVD) processes are widely used to form layers of materials on a semiconductor wafer. Other processing steps in the fabrication of the circuits include formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby leaving the metal layer in the form of the masked pattern; removing the mask layer using reactive plasma and chlorine gas, thereby exposing the top surface of the metal interconnect layer; cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate; and removing or stripping polymer residues from the wafer substrate.
CVD processes include thermal deposition processes, in which a gas is reacted with the heated surface of a semiconductor wafer substrate, as well as plasma-enhanced CVD processes, in which a gas is subjected to electromagnetic energy in order to transform the gas into a more reactive plasma. Forming a plasma can lower the temperature required to deposit a layer on the wafer substrate, to increase the rate of layer deposition, or both. However, in plasma process chambers used to carry out these various CVD processes, materials such as polymers are coated onto the chamber walls and other interior chamber components and surfaces during the processes. These polymer coatings frequently generate particles which inadvertently become dislodged from the surfaces and contaminate the wafers.
The chemical vapor deposition, etching and other processes used in the formation of integrated circuits on the wafer substrate are carried out in multiple process chambers. The process chambers are typically arranged in the form of an integrated cluster tool, in which multiple process chambers are disposed around a central transfer chamber equipped with a wafer transport system for transporting the wafers among the multiple process chambers. By eliminating the need to transport the wafers large distances from one chamber to another, cluster tools facilitate integration of the multiple process steps and improve wafer manufacturing throughput.
A typical conventional integrated cluster tool is generally indicated by reference numeral 10 in FIG. 1. An integrated cluster tool 10 such as a Centura HP 5200 tool sold by the Applied Materials Corp. of Santa Clara, Calif., includes one or a pair of adjacent loadlock chambers 12, each of which receives a wafer cassette or holder 13 holding multiple semiconductor wafers 28. The loadlock chambers 12 are flanked by an orientation chamber 14 and a cooldown chamber 16. Multiple process chambers 18 for carrying out various processes in the fabrication of integrated circuits on the wafers 28 are positioned with the orientation chamber 14, the cooldown chamber 16 and the loadlock chambers 12 around a central transfer chamber 20. A transfer robot 22 in the transfer chamber 20 is fitted with a transfer blade 24 which receives and supports the individual wafers 28 from the wafer cassette or holder 13 in the loadlock chamber 12. The transfer robot 22 is capable of rotating the transfer blade 24 in the clockwise or counterclockwise direction in the transfer chamber 20, and the transfer blade 24 can extend or retract to facilitate placement and removal of the wafers 28 in and from the load lock chambers 12, the orientation chamber 14, the cooldown chamber 16 and the process chambers 18.
In operation, the transfer blade 24 initially removes a wafer 28 from the wafer cassette 13 and then inserts the wafer 28 in the orientation chamber 14. The transfer robot 22 then transfers the wafer 28 from the orientation chamber 14 to one or more of the process chambers 18, where the wafer 28 is subjected to a chemical vapor deposition or other process. From the process chamber 18, the transfer robot 22 transfers the wafer 28 to the cooldown chamber 16, and ultimately, back to the wafer cassette or holder 13 in the loadlock chamber 12.
After they are processed in the various process chambers of the cluster tool, some of the wafers are sampled for inspection, with the sampling rate and selection method based on the process involved. Typically, the sampled wafers are transported from the cluster tool to an inspection station and inspected for surface defects, line width, electrical functions and the like. U.S. Pat. No. 6,424,733, details an apparatus which is incorporated into a cluster tool for the inspection of wafers.
It is known that some of the processes utilized in the integrated circuit fabrication process differ from each other in stability. The processes which are deemed most stable do not exhibit large variations in the process parameters over time after the parameters are initially adjusted to within the inspection criteria. Thus, the process chambers in which these processes are carried out may be able to operate for days at a time without the need for adjustments and fine-tuning to return the process parameters to within the predetermined specifications. Consequently, these stable processes do not require a high sampling rate for inspection. On the other hand, less stable processes are more likely to veer from within the predetermined specifications and thus, require frequent sampling in order for corrective measures to the processes to be taken.
Wafers are generally processed in lots each having from 20 to 25 wafers. If the sampling rate for a given process is low, the process may inadvertently veer from the preset specifications unbeknownst to the equipment operating personnel, in which case a large number of wafers having defects may complete processing. These defects may be caused by mechanical failures such as a blown o-ring or adverse processing phenomena such as electrical arcing, for example.
Another common cause of process-related defects induced in substrates includes the dislodging of etchant or deposition polymer material from the walls of the chamber onto the substrate. If this occurs early in the first lot or shortly after a sampling, for example, the defect-causing event may be eventually ascertained by facility personnel only after a large number of defect-laden substrates have been processed. While a higher sampling rate would enable personnel to discover the cause for the defects earlier in the process, sampling tends to inhibit productivity, and thus, is best avoided when possible.
Due to the ever-decreasing size of device features in fabricated integrated circuits, IC manufacturers are required to detect defects of corresponding reduced size. The defect detection equipment used for this purpose, however, is typically expensive and occupies an inordinately large footprint space. Moreover, transfer of the substrates from the process tool to an inspection station requires handling equipment which occupies additional footprint space and the operation of which may introduce additional contaminants onto the devices on the substrates. Accordingly, an apparatus is needed for the real-time visualization of operating conditions inside process chambers to enable personnel to take corrective action in the event that defect-precipitating events occur in the chamber during semiconductor processing.
An object of the present invention is to provide a novel apparatus for visualization of conditions inside a process chamber.
Another object of the present invention is to provide a novel apparatus which may be adapted to record real-time images of conditions inside a process chamber.
Still another object of the present invention is to provide a novel apparatus which may be adapted to visualize or monitor conditions inside multiple process chambers.
Yet another object of the present invention is to provide a novel apparatus which may be adapted to enable semiconductor fabrication facility personnel to troubleshoot various process conditions during the fabrication of semiconductor integrated circuits.
A still further object of the present invention is to provide a novel apparatus which may reduce the frequency of periodic maintenance for process chambers.
Still another object of the present invention is to provide a novel apparatus including an inspection chamber which may be installed adjacent to a process chamber and a camera provided in the inspection chamber for viewing process conditions in the process chamber.